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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-12541-1E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89930A Series
MB89935A/P935A/PV930A
s DESCRIPTION
The MB89930A series is a line of single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such, timers, a serial interface, an A/D converter and an external interrupt.
s FEATURES
* * * * * * * * * * * * * * MB89600 Series CPU core Maximum memory space: 64 Kbytes Minimum execution time: 0.4 s/10 MHz Interrupt processing time: 3.6 s/10 MHz I/O ports: max. 21channels 21-bit timebase timer 8-bit PWM timer 8/16-bit capture timer/counter 10-bit A/D converter: 8 channels UART 8-bit serial I/O External interrupt 1: 3 channels External interrupt 2: 8 channels Wild Register: 2 bytes
(Continued)
s PACKAGE
30-pin plastic SSOP 48-pin Ceramic MQFP
(FPT-30P-M02)
(MQP-48C-P01)
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MB89930A Series
(Continued) * Low-power consumption modes ( sleep mode, and stop mode) * SSOP-30 and MQFP-48 package * CMOS Technology
s PRODUCT LINEUP
Part number Parameter
MB89935A Mass production product (mask ROM product) 16 K x 8 bits (internal mask ROM) Number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time:
MB89P935A One-time PROM product (for small-scale production) 16 K x 8 bits (internal PROM) 512 x 8 bits 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.4 s to 6.4 s(10 MHz) 3.6 s to 57.6 s(10 MHz)
MB89PV930A Piggyback/evaluation product (for development) 32 K x 8 bits (external EPROM)
Classification ROM size RAM size
CPU functions
Ports 21-bit time base timer Watching timer
General-purpose I/O ports (CMOS): 21 (also serve as peripherals ) (4 ports are also an N-ch open-drain type.) 21-bit Interrupt cycle: 0.82, 3.3, 26.2, or 419.4 ms with 10-MHz main clock Reset generation cycle: 419.4 ms minimum with 10-MHz main clock 8-bit interval timer operation (square output capable, operating clock cycle: 0.4 s , 3.2 s ,6.4 s ,25.6 s) 8-bit resolution PWM operation (conversion cycle: 102.4s to 26.84s) Count clock selectable between 8-bit and 16-bit timer/counter outputs 8-bit capture timer/counter x 1 channel + 8-bit timer or 16-bit capture timer/counter x 1 channel Capable of event count operation and square wave output using external clock input with 8-bit timer 0 or 16-bit counter Transfer data length: 6/7/8 bits Transfer rate: 300 to 9600 bps/10 MHz 8 bits LSB first/MSB first selectable One clock selectable from four operation clocks (one external shift clock, three internal shift clocks: 0.8 s, 6.4 s, 25.6 s) Output frequency: Pulse width and cycle selectable 3 channels (Interrupt vector, request flag, request output enabled) Edge selectable (Rising edge, falling edge, or both edges) Also available for resetting stop/sleep mode (Edge detectable even in stop mode) 1 channel with 8 inputs (Independent L-level interrupt and input enable) Also available for resetting stop/sleep mode (Level detectable even in stop mode) 10-bit precision x 8 channels A/D conversion function (Conversion time : 15.2 s/10 MHz) Continuous activation by 8/16-bit timer/counter output or time-base timer counter
8-bit PWM timer
8/16-bit capture, timer/counter
UART
8-bit Serial I/O 12-bit PPG timer External interrupt 1 (wake-up function) External interrupt 2 (wake-up function) 10-bit A/D converter
(Continued)
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MB89930A Series
(Continued)
Part number Parameter
MB89935A
MB89P935A 8-bit x 2 Sleep mode, and Stop mode
MB89PV930A
Wild Register Standby mode *Power supply Voltage 2.2 V to 5.5 V
3.0 V to 5.5 V
2.7 V to 5.5 V
*: The minimum operating voltage varies with the operating frequency, the function, and the connected ICE.
s PACKAGE AND CORRESPONDING PRODUCTS
Package FPT-30P-M02 MQP-48C-P01 : Available x : Not available x x MB89935A MB89P935A MB89PV930A x*
* : Adapter for 48-pin to 30-pin conversion (manufactured by Sun Hayato Co., Ltd.) Part number : 48QF-30SOP-8L Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403
s DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used.
2. Current Consumption
In the case of the MB89PV930A, add the current consumed by the EPROM which is connected to the top socket.
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product. Before using options check section "s MASK OPTIONS" Take particular care on the following points: Options are fixed on the MB89PV930A and MB89P935A.
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MB89930A Series
s PIN ASSIGNMENT
(TOP VIEW)
P04/INT24 P05/INT25 P06/INT26 P07/INT27 MOD0 MOD1 RST X0 X1 VSS P37/BZ/PPG P36/INT12 P35/INT11 P34/TO/INT10 P33/EC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VCC P03/INT23/AN7 P02/INT22/AN6 P01/INT21/AN5 P00/INT20/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 AVSS P50/PWM P30/UCK/SCK P31/UO/SO P32/UI/SI C
(FPT-30P-M02)
(Continued)
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MB89930A Series
(Continued)
(TOP VIEW)
P35/INT11 N.C. N.C. N.C. N.C. N.C. VSS P34/TO/INT10 P33/EC P32/UI/SI P31/UO/SO P30/UCK/SCK P40/AN0 P41/AN1 P42/AN2 P43/AN3 P00/INT20/AN4 P01/INT21/AN5 P02/INT22/AN6 1 3 4 5 6 7 8 9 10 11 12 69 70 71 72 73 74 75 76
48 47 46 45 44 43 42 41 40 39 38 37 36 68 67 66 65 64 63 62 61 35 34 60 59 58 57 56 55 54 53 77 78 79 80 49 50 51 52 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24
N.C. N.C. N.C. N.C. N.C.
N.C. P36/INT12 P37/BZ/PPG X1 X0 RST MOD1 MOD0 P07/INT27 P06/INT26 P05/INT25 P04/INT24
2
P03/INT23/AN7 AVSS
(MQP-48C-P01)
Pin no. 49 50 51 52 53 54 55 56
Pin name VPP A12 A7 A6 A5 A4 A3 N.C.
Pin no. 57 58 59 60 61 62 63 64
Pin name N.C. A2 A1 A0 O1 O2 O3 VSS
Pin no. 65 66 67 68 69 70 71 72
N.C. N.C. N.C. N.C. N.C. P50/PWM
N.C. N.C. N.C. VCC
Pin name O4 O5 O6 O7 O8 CE A10 N.C.
Pin no. 73 74 75 76 77 78 79 80
Pin name OE N.C. A11 A9 A8 A13 A14 VCC
N.C.: Internally connected. Do not use. 5
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MB89930A Series
s PIN DESCRIPTION
Pin No. SSOP*1 MQFP*2 8 9 5 6 32 33 29 30 X0 X1 MOD0 MOD1 Pin name Circuit type A B Function Pins for connecting the crystal resonator for the main clock. To use an eternal clock, input the signal to X0 and leave X1 open. Memory access mode setting input pins. Connect the pin directly to Vss. Reset I/O pin. This pin serves as an N-channel open-drain output with pull-up resistor and a hysteresis input as well. The pin outputs the "L" signal (optionally) in response to an internal reset request. Also, it initializes the internal circuit upon input of the "L" signal. General-purpose CMOS I/O ports. These pins also serve as an input (wake-up input) of external interrupt 2 or as an A/D converter analog input. The input of external interrupt 2 is a hysteresis input. General-purpose CMOS I/O ports. These pins also serve as an input (wake-up input) of external interrupt 2. The input of external interrupt 2 is a hysteresis input. General-purpose CMOS I/O ports. This pin also serves as the clock I/O pin for the UART or 8-bit serial I/O. The resource is a hysteresis input. General-purpose CMOS I/O ports. This pin also serves as the data output pin for the UART or 8bit serial I/O. General-purpose CMOS I/O ports. This pin also serves as the data input pin for the UART or 8-bit serial I/O. The resource is a hysteresis input. General-purpose CMOS I/O ports. This pin also serves as the external clock input pin for the 8/16bit capture timer/counter. The resource is a hysteresis input. General-purpose CMOS I/O ports. This pin also serves as the output pin for the 8/16-bit capture timer/counter or as the input pin for external interrupt 1. The resource is a hysteresis input. General-purpose CMOS I/O ports. These pins also serve as the input pin for external interrupt 1. The resource is a hysteresis input. General-purpose CMOS I/O ports. This pin also serves as the buzzer output pin or the 12-bit programmable pulse generator output.
7
31
RST
C
P00/INT20/AN4 26 to 29 10 to 13 to P03/INT23/AN7
G
1 to 4
P04/INT24 to 25 to 28 P07/INT27
D
19
5
P30/UCK/SCK
D
18
4
P31/UO/SO
E
17
3
P32/UI/SI
D
15
2
P33/EC
D
14
1
P34/TO/INT10
D
13, 12
48,35
P35/INT11, P36/INT12
D
11
34
P37/BZ/PPG
E
(Continued)
*1: FPT-30P-M02 *2: MQP-48C-P01 6
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MB89930A Series
(Continued)
Pin No. SSOP* 20
1
MQFP* 24
2
Pin name
Circuit type E
Function General-purpose CMOS I/O ports. This pin also serves as the 8-bit PWM output pin. The pin is a hysteresis input. General-purpose CMOS I/O ports. These pins can also be used as N-channel open-drain ports. The pins also serve as A/D converter analog input pins. Power supply pin Power (GND) pin Power supply pin for the A-D converter. Apply equal potential to this pin and the VSS pin. Capacitance pin for regulating the power supply. Connect an external ceramic capacitor of about 0.1F.
P50/PWM
22 to 25 30 10 21 16
6 to 9 18 42 14 --
P40/AN0 to P43/AN3 VCC VSS AVSS C
F -- -- -- --
*1: FPT-30P-M02 *2: MQP-48C-P01
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MB89930A Series
s EXTERNAL EPROM PIN DESCRIPTION (MB89PV930A only)
Pin No. 49 50 51 52 53 54 55 58 59 60 61 62 63 64 65 66 67 68 69 70 71 73 75 76 77 78 79 80 56 57 72 74 Pin name VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS O4 O5 O6 O7 O8 CE A10 OE A11 A9 A8 A13 A14 VCC I/O O "H" level output pin Function
O
Address output pins
I O
Data input pins Power supply (GND) pin
I
Data input pins
O O O
ROM chip enable pin Outputs "H" during standby. Address output pin ROM output enable pin Outputs "L" at all times.
O
Address output pins
O
EPROM power supply pin Internally connected pins Be sure to leave them open.
N.C.
--
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MB89930A Series
s I/O CIRCUIT TYPE
Type Circuit Remarks * Crystal oscillation type
X1
A
X0
Standby control signal * Hysteresis input B * At an output pull-up resister (P-ch) of approximately 50k/5.0 V * Hysteresis input
P-ch
C
N-ch
P-ch
* * * *
P-ch
CMOS output CMOS input Hysteresis input (Resource input) Pull-up resistor optional
D
N-ch
(Continued)
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MB89930A Series
(Continued)
Type Circuit Remarks * CMOS output * CMOS input * Pull-up resistor optional
P-ch
P-ch
E
N-ch
P-ch
open-drain control
* * * *
CMOS output CMOS input Analog input N-ch open-drain output available
F
N-ch
Analog input
A/D enable * * * *
P-ch
P-ch
CMOS output CMOS input Hysteresis input (Resouce input) Analog input
G
N-ch
Analog input
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MB89930A Series
s HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on "1. Absolute Maximum Ratings" in section "s ELECTRICAL CHARACTERISTICS" is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor of at least 2 kilohms between the pin and the power supply.
3. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
4. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
5. Treatment of Power Supply Pins on Microcontrollers with A/D Converters
Connect to be AVSS = VSS even if the A/D converters are not in use.
6. Precautions when Using an External Clock
When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and wake-up from stop mode.
7. About the Wild Register Function
No wild register can be debugged on the MB89PV930A. For the operation check, test the MB89P935A installed on a target system.
8. Program Execution in RAM
When the MB89PV930A is used, no program can be executed in RAM.
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MB89930A Series
s PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TVM
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Package LCC-32 Compatible socket part number ROM-32LC-28DP-S
Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403 FAX (81)-3-5396-9106
3. Memory Space.
Normal operating mode Address
0000H I/O 0080H RAM 512 B 0280H
Not available
Corresponding adresses on the ROM programmer Address
8000H
0000H
PROM 32 KB
EPROM 32 KB
FFFFH
7FFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0000H to 7FFFH. (3) Program to 0000H to 7FFFH with the EPROM programmer.
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MB89930A Series
s PROGRAMMING TO THE OTPROM WITH MB89P935A
1. Memory Space
Normal operating mode Address
0000H I/O 0080H RAM 512 B 0280H
Not available
Corresponding adresses on the ROM programmer Address
C000H
C000H
PROM 16 KB
PROM 16 KB
FFFFH
FFFFH
2. Programming to the OTPROM
To program to the OTPROM using an EPROM programmer AF200 (manufacturer: Yokogawa Digital Computer Corp.) . Inquiry : Yokogawa Digital Computer Corp. : TEL (81) -42-333-6224 Note : Programming to the OTPROM with MB89P935A is serial programming mode only.
3. Programming Adaptor for OTPROM
To program to the OTPROM using an EPROM programmer AF200, use the programming adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Adaptor socket : ROM3-FPT30M02-8L Inquiry : Sun Hayato Co., Ltd. : TEL (81) -3-3986-0403 FAX (81) -3-5396-9106
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MB89930A Series
s BLOCK DIAGRAM
X0 X1
Main clock oscillator
Timebase timer
Clock controller
CMOS I/O port
Port 5
RST
Reset circuit
8 bit PWM
P50 / PWM
CMOS I/O port
UART prescaler
Port 0
UART
Serial function switching
Internal bus
P04 / INT24 P07 / INT27
4
8
External interrupt2 (wake-up)
P00 / INT20 / AN4 4 P03 / INT23 / AN7
4
P30 / UCK / SCK P31 / UO / SO P32 / UI / SI
8 bit serial I/O
10 bit A/D Converter
AVSS
4
Port 4
Port 3
8/16 bit capture timer/ counter
P33 / EC P34 / TO / INT10
P40 / AN0 4 P43 / AN3
CMOS I/O port (N-ch OD) 512 byte RAM
Exernal interrupt 1
3
2
P35 / INT11 P36 / INT12
12 bit PPG F2MC - 8 L CPU P37 / BZ / PPG
Other pins
VCC, VSS, MOD1, MOD0, C
16 Kbyte ROM
Buzzer output
Wild register
CMOS I/O port
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MB89930A Series
s CPU CORE
1. Memory Space
The microcontrollers of the MB89930A series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89930A series is structured as illustrated below. * Memory Space
MB89935A 0000H I/O 0080H RAM 512 B 0100H 0100H 0080H RAM 512 B 0100H 0000H I/O 0080H RAM 512 B MB89P935A 0000H I/O MB89PV930A
Register
0200H 0280H
Register
0200H 0280H
0200H 0280H
Not available
Not available
8000H
Not available
C000H ROM 16 KB FFFFH
C000H PROM 16 KB FFFFH FFFFH
External EPROM 32 KB
Register
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MB89930A Series
2. Registers
The MB89930A series has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): Accumulator (A): Temporary accumulator (T): Index register (IX): Extra pointer (EP): Stack pointer (SP): Program status (PS):
16 bit
PC A T IX EP SP RP PS CCR
A 16-bit register for indicating instruction storage positions A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register for index modification A 16-bit pointer for indicating a memory address A 16-bit register for indicating a stack area A 16-bit register for storing a register pointer, a condition code Initial value : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status FFFDH Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate I-flag = 0, IL1, 0 = 11 The other bit values are indeterminate.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) * Structure of the Program Status Register
RP bit15 bit14 bit13 bit12 bit11 bit10 bit9 R4 R3 R2 R1 R0 - - H-flag I-flag IL1,0 N-flag Z-flag bit8 - bit7 H bit6 I bit5 IL1 CCR bit4 IL0 bit3 N bit2 Z bit1 V bit0 C
CCR initial value
X011XXXXB
PS
x : Undefined
V-flag C-flag
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MB89930A Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. * Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
"0" "0" "0" "0" "0" "0" "0" A9 "1" A8 R4 A7 R3 A6 R2 A5 R1 A4 R0 A3
Low OP codes
b2 A2 b1 A1 b0 A0
Generated addresses
A15 A14 A13 A12 A11 A10
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag:Set to `1' when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to `0' otherwise. This flag is for decimal adjustment instructions. I-flag: Interrupt is enabled when this flag is set to `1'. Interrupt is disabled when the flag is cleared to `0'. Cleared to `0' at the reset. IL1, 0:Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 0 0 1 1 IL0 0 1 0 1 Interrupt level 1 2 3 Low = no interrupt High-low High
N-flag:Set to `1' if the MSB becomes to `1' as the result of an arithmetic operation. Cleared to `0' when the bit is cleared to `0'. Z-flag:Set to `1' when an arithmetic operation results in 0. Cleared otherwise. V-flag:Set to `1' if the complement on 2 overflows as a result of an arithmetic operation. Cleared to `0' if the overflow does not occur. C-flag:Set to `1' when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to `0' otherwise. Set to the shift-out value in the case of a shift instruction.
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MB89930A Series
The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 16 banks can be used on the MB89930A series. The bank currently in use is indicated by the register bank pointer (RP).. * Register Bank Configuraiton
This address = 0100H + 8 x (RP)
R0 R1 R2 R3 R4 R5 R6 R7
16 banks
Memory area
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MB89930A Series
s I/O MAP
Address 0000H 0001H 0002H to 00006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H 001AH 001BH 001CH 001DH 001EH 001FH 0020H 0021H 0022H 0023H 00024H CNTR COMR EIC1 PWM control register PWM compare register External interrupt 1 Control register 1 PDR3 DDR3 RSFR PDR4 DDR4 OUT4 PDR5 DDR5 RCR21 RCR22 RCR23 RCR24 BZCR TCCR TCR1 TCR0 TDR1 TDR0 TCPH TCPL TCR2 Port 3 data register Port 3 data direction register Reset flag register Port 4 data register Port 4 data direction register Port 4 output format register Port 5 data register Port 5 data direction register 12-bit PPG control register 1 12-bit PPG control register 2 12-bit PPG control register 3 12-bit PPG control register 4 Buzzer register Capture control register Timer 1 control register Timer 0 control register Timer 1 data register Timer 0 data register Capture data register H Capture data register L Timer output control register Vacancy R/W W R/W 0 - 0000 0 0 X X XXXX X X 000000 0 0 SYCC STBC WDTC TBTC Register name PDR0 DDR0 Register description Port 0 data register Port 0 data direction register Vacancy System clock control register Standby control register Watchdog timer control register Timebase timer control register Vacancy R/W W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W X X XXXX X X 000000 0 0 XXXX- - - - - - - XXXX - - - - 0000 - - - - 0000 -------X -------0 000000 0 0 - - 0000 0 0 0 - 0000 0 0 - - 0000 0 0 - - ---000 000000 0 0 000000 0 0 000000 0 0 X X XXXX X X X X XXXX X X X X XXXX X X X X XXXX X X ------00 R/W R/W W R/W 1 - - MM 1 0 0 00010 - - 0 - - - XXXX 00---000 Read/write R/W W Initial value X X XXXX X X 000000 0 0
(Continued)
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MB89930A Series
(Continued)
Address 0025H 0026H 0027H 0028H 0029H 002AH 002BH 002CH 002DH to 0002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH to 003FH 0040H 0041H 0042H 0043H 0044H 0045H 0046H 0047H 0048H to 006FH 0070H PUL0 WRARH1 WRARL1 WRDR1 WRARH2 WRARL2 WRDR2 WREN WROR SMR SDR SSEL Serial mode register Serial data register Serial function switching register Vacancy Upper-address setting register 1 Lower-address setting register 1 Data setting register 1 Upper-address setting register 2 Lower-address setting register 2 Data setting register 2 Wild-register enable register Wild-register data test register Vacancy Port-0 pull-up setting register R/W 000000 0 0 R/W R/W R/W R/W R/W R/W R/W R/W X X XXXX X X X X XXXX X X X X XXXX X X X X XXXX X X X X XXXX X X X X XXXX X X X X XXXX 0 0 ------00 EIE2 EIF2 ADC1 ADC2 ADDH ADDL ADEN SMC SRC SSD SIDR SODR UPC Register name EIC2 Register description External interrupt 1 Control register 2 Vacancy Serial mode control register Serial rate control register Serial status and data register Serial input data register Serial output data register Clock division selection register Vacancy A/D converter control register 1 A/D converter control register 2 A/D converter data register H A/D converter data register L A/D enable register Vacancy External interrupt 2 control register1 External interrupt 2 control register2 Vacancy R/W R/W R/W 000000 0 0 X X XXXX X X -------0 R/W R/W 000000 0 0 -------0 R/W R/W R/W R/W R/W - 00000 0 0 - 00000 0 1 - - - - - - XX X X XXXX X X 000000 0 0 R/W R/W R/W R W R/W 00000 - 0 0 - - 0110 0 0 00100 - 1X X X XXXX X X 111111 1 1 - - - - 0010 Read/write R/W Initial value - - - - 0000
(Continued)
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MB89930A Series
(Continued)
Address 0071H 0072H 0073H to 007AH 007BH 007CH 007DH 007EH 007FH ILR1 ILR2 ILR3 ILR4 ITR Register name PUL3 PUL5 Register description Port-3 pull-up setting register Port-5 pull-up setting register Vacancy Interrupt level setting register1 Interrupt level setting register2 Interrupt level setting register3 Interrupt level setting register4 Interrupt test register W W W W Not available 111111 1 1 111111 1 1 111111 1 1 111111 1 1 ------00 Read/write R/W R/W Initial value 000000 0 0 -------0
- : Unused, X : Undefined, M : Set using the mask option Note: Do not use vacancies.
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MB89930A Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Power supply voltage Input voltage Output voltage "L" level maximum output current "L" level average output current "L" level total maximum output current "H" level maximum output current "H" level average output current "H" level total maximum output current Power consumption Operating temperature Storage temperature Symbol VCC VI VO IOL1 IOL2 IOLAV IOL IOH IOHAV IOH Pd Ta Tstg Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 -- -- -- -- -- -- -- -- -40 -55 Max. VSS + 6.0 VCC + 0.3 VCC + 6.0 20 10 4 100 -10 -2 -50 200 +85 +150 Unit V V V mA mA mA mA mA mA mA mW C C Average value (operating current x operating rate) Pins P40 to P43 Pins excluding P40 to P43 Average value (operating current x operating rate) Remarks
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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MB89930A Series
2. Recommended Operating Conditions
Parameter Symbol Value Min. 2.2 1.5 VIH "H" level input voltage VIHS VIL "L" level input voltage VILS Open-drain output pin application voltage Operating temperature VD Ta VSS - 0.3 VSS - 0.3 -40 0.2 VCC VCC + 0.3 +85 V V C 0.8 VCC VSS - 0.3 VCC + 0.3 0.3 VCC V V 0.7 VCC Max. 5.5 6.0 VCC + 0.3 Unit V V V Remarks Normal operation assurance range MB89935A Retains the RAMstate in stop mode P00 to P07, P30 to P37, P40 to P43, P50, UI/SI MOD0/1, RST, EC, INT20 to INT27, UCK/SCK, INT10 to INT12 P00 to P07, P30 to P37, P40 to P43, P50, UI/SI MOD0/1, RST, EC, INT20 to INT27, UCK/SCK, INT10 to INT12 P40 to P43
Power supply voltage
VCC
6
5
Analog accuracy assurance range
Operating voltage (V)
4
Operation assurance range
3
2
: Area is assured only for the MB89935A
1
0
1
2
3
4
5
6
7
8
9
10
Operating Frequency(MHz)
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating conditionranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 23
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MB89930A Series
3. DC Characteristics
(VCC = 5.0 V 10 %, AVSS = VSS = 0.0 V, FCH = 10 MHz(External clock), Ta = -40C to +85C) Parameter
Symbol
Pin name P00 to P07, P30 to P37, P40 to P43, P50 , UI/SI RST,MOD0/1, UCK/SCK, EC, INT20 to INT27, INT10 to INT12 P00 to P07, P30 to P37, P40 to P43, P50 , UI/SI RST,MOD0/1, UCK/SCK, EC, INT20 to INT27, INT10 to INT12
Condition
Value Min. 0.7 VCC Typ. -- Max. VCC + 0.3
Unit
Remarks
VIH "H" level input voltage VIHS
--
V
--
0.8 VCC
--
VCC + 0.3
V
VIL "L" level input voltage VILS
--
VSS - 0.3
--
0.3 VCC
V
--
VSS - 0.3
--
0.2 VCC
V
Open-drain output pin application voltage "H" level output voltage "L" level output voltage Input leakage current Pull-up resistance
VD
P40 to P43
--
VSS - 0.3
--
VCC + 0.3
V
VOH VOL1 VOL2 ILI
P00 to P07, P30 to P37, P40 to P43, P50 P00 to P07, P30 to P37, P50, RST P40 to P43 P00 to P07, P30 to P37, P40 to P43, P50 , MOD0/1 P00 to P07, P30 to P37, P40 to P43, P50
IOH = -4.0 mA IOL = 4.0 mA IOL = 12.0 mA 0.45 V < VI < VCC
2.4 -- -- --
-- -- -- --
-- 0.4 0.4 5 100 12 9 15 12 6 5 1 10
V V V Without A pull-up resistor mA MB89935A mA MB89P935A mA MB89935A mA MB89P935A mA MB89935A mA MB89P935A A MB89935A A MB89P935A pF MB89P935A
RPULL
VI = 0.0 V
25
50 8 6 10 8 4 3 10
ICC
When A/D Normal operation converter stops mode (External clock, When A/D highest gear speed) converter starts VCC Sleep mode When A/D (External clock, converter stops highest gear speed) Stop mode Ta = +25C (External clock) Other than AVSS, VCC, VSS When A/D converter stops
Power supply current
ICCS
ICCH Input capacitance
CIN
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MB89930A Series
4. AC Characteristics
(1) Reset Timing (AVSS = VSS = 0.0 V, Ta = -40C to +85C) Parameter RST "L" pulse width tHCYL : 1 oscillating clock cycle time Symbol tZLZH Condition -- Value Min. 16 tHCYL Max. -- Unit ns Remarks
tZLZH
RST
0.2 VCC 0.2 VCC
Note: When the power-on reset option is not on, leave the external reset on until oscillation becomes stable.
(2) Power-on Reset (AVSS = VSS = 0.0 V, Ta = -40C to +85C) Parameter Power supply rising time Power supply cutoff time Symbol tR tOFF Condition -- Value Min. -- 1 Max. 50 -- Unit ms ms Due to repeated operations Remarks
tR 2.0 V
tOFF
VCC
0.2 V
0.2 V
0.2 V
Note: The supply voltage must be set to the minimum value required for operation within the prescribed default oscillation settling time.
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MB89930A Series
(3) Clock Timing (AVSS = VSS = 0.0 V, Ta = -40C to +85C) Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time Symbol FCH tXCYL tWH tWL tCR tCF -- Condition Value Min. 1 100 20 -- Max. 10 1000 -- 10 Unit MHz ns ns ns Remarks
* X0 and X1 Timing and Conditions
tXCYL tWH tCR tCF 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC tWL
X0
* Main Clock Conditions When a crystal or ceramic resonator is used When an exernal clock is used
X0
X1
X0
X1
open
(4) Instruction Cycle. Parameter Instruction cycle (minimum execution time) Symbol tINST Value (typical) 4/FCH, 8/FCH, 16/FCH, 64/FCH Unit s Remarks tINST = 0.4 s when operating at FCH = 10 MHz (4/FCH)
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MB89930A Series
(5) Recommended Resonator Manufactures * Sample application of ceramic resonator
X0 R
X1
C1
C2
Resonator manufacturer
Resonator CSTS0400MG06 CSTCC4.00MG0H6 CSTS0800MG06 CSTCC8.00MG0H6 CST10.0MTW CSTCC10.0MG0H6
Frequency (MHz) 4.00 4.00 8.00 8.00 10.00 10.00
C1 Built-in Built-in Built-in Built-in Built-in Built-in
C2 Built-in Built-in Built-in Built-in Built-in Built-in
R 330 330 Not required Not required Not required Not required
Murata Mfg. Co., Ltd.
Inquiry : Murata Mfg. Co., Ltd. * Murata Electronics North America, Inc. : TEL1-404-436-1300 * Murata Europe Management GmbH : TEL 49-911-66870 * Murata Electronics Singapore (Pte.) : TEL 65-758-4233
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MB89930A Series
(6) Peripheral Input Timing
(VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, Ta = -40 C to +85 C) Symbol tILIH tIHIL Pin name INT10 to INT12, INT20 to INT27, EC Value Min. 2 tINST* 2 tINST* Max. Unit s s Remarks
Parameter Peripheral input "H" pulse width Peripheral input "L" pulse width
* : For information on tINST see "(4) Instruction Cycle".
tILIH
tIHIL
INT10 to INT12, INT20 to INT27, EC
0.8 VCC
0.8 VCC 0.2 VCC 0.2 VCC
(VCC = 5 V 10%, AVSS = VSS = 0.0 V, Ta = -40 C to +85 C) Parameter Peripheral input "H" noise limit Peripheral input "L" noise limit Symbol tIHNC tILNC Pin name INT10 to INT12, EC Value Min. 7 7 Typ. 15 15 Max. 23 23 Unit ns ns Remarks
tIHNC
tILNC
INT10 to INT12, EC
0.8 VCC
0.8 VCC 0.2 VCC 0.2 VCC
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MB89930A Series
(7) UART, Serial I/O Timing
(VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, Ta = -40 C to +85 C) Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name UCK/SCK UCK/SCK, SO Internal shift UCK/SCK, SI clock mode UCK/SCK, SI UCK/SCK UCK/SCK UCK/SCK, SO UCK/SCK, SI UCK/SCK, SI External shift clock mode Condition Value Min. 2 tINST -200 1/2 tINST 1/2 tINST tINST tINST 0 1/2 1/2 tINST tINST Max. 200 200 Unit Remarks s ns s s s s ns s s
Parameter Serial clock cycle time UCK/SCK SO time Valid SI UCK/SCK UCK/SCK Valid SI hold time Serial clock "H" pulse width Serial clock "L" pulse width UCK/SCK SO time Valid SI UCK/SCK UCK/SCK Valid SI hold time
*: For information on tinst, see "(4) Instruction Cycle". * Internal Shift Clock Mode
tSCYC 2.4 V
UCK/SCK
0.8 V tSLOV
0.8 V
SO
2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC
SI
0.8 VCC 0.2 VCC
* External Shift Clock Mode
tSLSH tSHSL 0.8 VCC 0.8 VCC
UCK/SCK
0.2 VCC 0.2 VCC tSLOV
SO
2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC
SI
0.8 VCC 0.2 VCC
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MB89930A Series
5. A/D Converter (1) A/D Converter Electrical Characteristics
(VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, Ta = -40 C to +85 C) Value Min. -5.0 -3.0 -2.5 VOT VFST IAIN VCC - 6.5 LSB 0 Typ. VCC - 1.5 LSB Max. 10 +5.0 +3.0 +2.5 VCC + 2.0 LSB 38 tINST 10 VCC Unit bit LSB LSB LSB V V s A V Remarks
Parameter Resolution Total error Linearity error Differential linearity error Zero transition voltage Full-scale transition voltage A/D mode conversion time Analog port input current Analog input voltage range
Symbol
AVSS - 3.5 LSB AVSS + 0.5 LSB AVSS + 4.5 LSB
* For information on tinst, see "(4) Instruction Cycle" in "4. AC Characteristics." (2) A/D Converter Glossary * Resolution Analog changes that are identifiable with the A/D converter When the number of bits is 10, analog voltage can be divided into 210 = 1024. * Linearity error (unit: LSB) The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1111" "11 1111 1110") from actual conversion characteristics * Differential linearity error (unit: LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value * Total error (unit: LSB) The difference between theoretical and actual conversion values
Digital output 11 1111 1111 11 1111 * 1110
* * * * * * * * * * * * * * * * * * *
Theoretical conversion value Actual conversion value (1 LSB x N + VOT) VCC 1024 VNT - (1 LSB x N + VOT) 1 LSB V( N + 1 ) T - VNT -1 1 LSB VNT - (1 LSB x N + 1 LSB) 1 LSB
1 LSB =
Linearity error = Differential linearity error = Total error = 0010 0001 0000 VOT VNT V(N + 1)T VFST Analog input
Linearity error
00 0000 00 0000 00 0000
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MB89930A Series
(3) Notes on Using A/D Converter * Input impedance of the analog input pins The A/D converter used for the MB89930A series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for 16 instruction cycles after activating A/D conversion. For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output impedance of the external circuit low (below 4 k). Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 F for the analog input pin. Analog Input Equivalent Circuit Sample hold circuit Analog input pin Comparator
R C
If the analog input impedance is higher than 4 k, it is recommended to connect an external capacitor of approx. 0.1 F.
Close for 16 instruction cycles after activating A/D conversion Analog channel selector
* Error The smaller the | VCC - AVSS |, the greater the error would become relatively.
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MB89930A Series
s EXAMPLE CHARACTERISTICS
* Power Supply Current (MB89935A : External Clock Mode) MB89935A At the Main Clock Operation (ICC1 - VCC, ICC2 - VCC)
ICC (mA) 8
MB89935A At the Main Sleep Mode (ICCS1 - VCC, ICCS2 - VCC)
ICCS (mA) (FCH = 10 MHz, Ta = +25 C) 4
(FCH = 10 MHz, Ta = +25 C)
6
3
ICC1 (highest gear speed)
4
2
ICC1 (highest gear speed)
2
1
ICC2 (lowest gear speed)
ICC2 (lowest gear speed)
0 0 2 3 4 5 6 VCC (V)
0 0 2 3 4 5 6 VCC (V)
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MB89930A Series
s INSTRUCTIONS (136 INSTRUCTIONS)
Execution instructions can be divided into the following four groups: * Transfer * Arithmetic operation * Branch * Others Table 1 lists symbols used for notation of instructions. Table 1 Symbol dir off ext #vct #d8 #d16 dir: b rel @ A AH AL T TH TL IX EP PC SP PS dr CCR RP Ri x (x) (( x )) Instruction Symbols Meaning Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits) Immediate data (16 bits) Bit direct address (8:3 bits) Branch relative address (8 bits) Register indirect (Example: @A, @IX, @EP) Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of accumulator A (8 bits) Lower 8 bits of accumulator A (8 bits) Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of temporary accumulator T (8 bits) Lower 8 bits of temporary accumulator T (8 bits) Index register IX (16 bits) Extra pointer EP (16 bits) Program counter PC (16 bits) Stack pointer SP (16 bits) Program status PS (16 bits) Accumulator A or index register IX (16 bits) Condition code register CCR (8 bits) Register bank pointer RP (5 bits) General-purpose register Ri (8 bits, i = 0 to 7) Indicates that the very x is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Indicates that the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) The address indicated by the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: The number of instructions #: The number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: * "-" indicates no change. * dH is the 8 upper bits of operation description data. * AL and AH must become the contents of AL and AH prior to the instruction executed. * 00 becomes 00. N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F This indicates 48, 49, ... 4F. 33
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MB89930A Series
Table 2 Mnemonic MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP ,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP ,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A MOVW ext,A MOVW @EP ,A MOVW EP ,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP ,#d16 MOVW IX,A MOVW A,IX MOVW SP ,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP ,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC Note ~ 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 # 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 Transfer Instructions (48 instructions) Operation (dir) (A) ( (IX) +off ) (A) (ext) (A) ( (EP) ) (A) (Ri) (A) (A) d8 (A) (dir) (A) ( (IX) +off) (A) (ext) (A) ( (A) ) (A) ( (EP) ) (A) (Ri) (dir) d8 ( (IX) +off ) d8 ( (EP) ) d8 (Ri) d8 (dir) (AH),(dir + 1) (AL) ( (IX) +off) (AH), ( (IX) +off + 1) (AL) (ext) (AH), (ext + 1) (AL) ( (EP) ) (AH),( (EP) + 1) (AL) (EP) (A) (A) d16 (AH) (dir), (AL) (dir + 1) (AH) ( (IX) +off), (AL) ( (IX) +off + 1) (AH) (ext), (AL) (ext + 1) (AH) ( (A) ), (AL) ( (A) ) + 1) (AH) ( (EP) ), (AL) ( (EP) + 1) (A) (EP) (EP) d16 (IX) (A) (A) (IX) (SP) (A) (A) (SP) ( (A) ) (T) ( (A) ) (TH),( (A) + 1) (TL) (IX) d16 (A) (PS) (PS) (A) (SP) d16 (AH) (AL) (dir): b 1 (dir): b 0 (AL) (TL) (A) (T) (A) (EP) (A) (IX) (A) (SP) (A) (PC) TL - - - - - AL AL AL AL AL AL AL - - - - - - - - - AL AL AL AL AL AL - - - - - - - - - - - - - - - AL AL - - - - TH - - - - - - - - - - - - - - - - - - - - - AH AH AH AH AH AH - - - - - - - - - - - - - - - - AH - - - - AH - - - - - - - - - - - - - - - - - - - - - dH dH dH dH dH dH dH - - dH - dH - - - dH - - AL - - - dH dH dH dH dH NZVC ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++++ ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- OP code 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 D4 D7 E3 E4 C5 C6 C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0
During byte transfer to A, T A is restricted to low bytes. Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family)
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MB89930A Series
Table 3 Mnemonic ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A ROLC A CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir ~ 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 # 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation (A) (A) + (Ri) + C (A) (A) + d8 + C (A) (A) + (dir) + C (A) (A) + ( (IX) +off) + C (A) (A) + ( (EP) ) + C (A) (A) + (T) + C (AL) (AL) + (TL) + C (A) (A) - (Ri) - C (A) (A) - d8 - C (A) (A) - (dir) - C (A) (A) - ( (IX) +off) - C (A) (A) - ( (EP) ) - C (A) (T) - (A) - C (AL) (TL) - (AL) - C (Ri) (Ri) + 1 (EP) (EP) + 1 (IX) (IX) + 1 (A) (A) + 1 (Ri) (Ri) - 1 (EP) (EP) - 1 (IX) (IX) - 1 (A) (A) - 1 (A) (AL) x (TL) (A) (T) / (AL),MOD (T) (A) (A) (T) (A) (A) (T) (A) (A) (T) (TL) - (AL) (T) - (A) CA C A (A) - d8 (A) - (dir) (A) - ( (EP) ) (A) - ( (IX) +off) (A) - (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) TL - - - - - - - - - - - - - - - - - - - - - - - dL - - - - - - - - - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - - - - - - - - - 00 - - - - - - - - - - - - - - - - - - - - - - - AH - - - - - dH - - - - - - dH - - - - dH - - - dH dH 00 dH dH dH - - - - - - - - - - - - - - - - - - - - NZVC ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++- ---- ---- ++-- +++- ---- ---- ++-- ---- ---- ++R- ++R- ++R- ++++ ++++ ++-+ ++-+ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- OP code 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65
(Continued)
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MB89930A Series
(Continued) Mnemonic
AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP ,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP
~ 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3
# 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1
Operation (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (dir) - d8 ( (EP) ) - d8 ( (IX) + off) - d8 (Ri) - d8 (SP) (SP) + 1 (SP) (SP) - 1 Table 4
TL - - - - - - - - - - - - - - -
TH - - - - - - - - - - - - - - -
AH - - - - - - - - - - - - - - -
NZVC ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++++ ++++ ++++ ++++ ---- ----
OP code 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1
Branch Instructions (17 instructions) Operation TL - - - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - - - AH - - - - - - - - - - - - - - dH - - NZVC ---- ---- ---- ---- ---- ---- ---- ---- -+-- -+-- ---- ---- ---- ---- ---- ---- Restore OP code FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30
Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI
~ 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6
# 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1
If Z = 1 then PC PC + rel If Z = 0 then PC PC + rel If C = 1 then PC PC + rel If C = 0 then PC PC + rel If N = 1 then PC PC + rel If N = 0 then PC PC + rel If V N = 1 then PC PC + rel If V N = 0 then PC PC + reI If (dir: b) = 0 then PC PC + rel If (dir: b) = 1 then PC PC + rel (PC) (A) (PC) ext Vector call Subroutine call (PC) (A),(A) (PC) + 1 Return from subrountine Return form interrupt Table 5
Other Instructions (9 instructions) Operation TL - - - - - - - - - TH - - - - - - - - - AH - dH - - - - - - - NZVC ---- ---- ---- ---- ---- ---R ---S ---- ---- OP code 40 50 41 51 00 81 91 80 90
Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI
~ 4 4 4 4 1 1 1 1 1
# 1 1 1 1 1 1 1 1 1
36
H
3 RETI PUSHW POPW MOV MOVW CLRI A A A,ext A,PS SETC SETI CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC 4 5 6 7 8 9 A B C D E F
L
0
1
2
0
NOP
SWAP
RET
1
MULU
DIVU
A SUBC A A A, T A A A XCH XOR AND OR
A
JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A
CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP ,A A,SP
2
ROLC
CMP
ADDC
s INSTRUCTION MAP
A
A
MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX
3
RORC
CMPW
A XOR AND OR DAA A,#d8 A,#d8 A,#d8 DAS
A
ADDCW SUBCW XCHW XORW ANDW ORW MOVW MOVW CLRB BBC INCW DECW MOVW MOVW A A A, T A A A @A,T A,@A dir: 3 dir: 3,rel EP EP EP ,A A,EP CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC
4
MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8
5
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP ,#d16 A,SP
6
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8 dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16 A,IX
7
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@EP A,@EP A,@EP A,@EP @EP ,A A,@EP A,@EP A,@EP @EP ,#d8 @EP ,#d8 dir: 7 dir: 7,rel A,@EP @EP ,A EP ,#d16 A,EP DEC R0 DEC R1 DEC R2 DEC R3 DEC R4 DEC R5 DEC R6 DEC R7 R7 R6 R5 R4 R3 R2 R1 R0 CALLV BNC #0 rel CALLV BC #1 CALLV BP #2 CALLV BN #3
8
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel
9
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel
rel
A
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel
rel
B
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel
rel CALLV BNZ #4 rel CALLV BZ #5
C
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel
D
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel
rel CALLV BGE #6 rel CALLV BLT #7
E
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel
F
MB89930A Series
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel
rel
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37
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MB89930A Series
s MASK OPTIONS
Part number No Specifying procedure Selection of initial value of main clock oscillation settling time* ( with FCH = 10 MHz) 01 : 214/FCH (Approx.1.63 ms) 10 : 217/FCH (Approx.13.1 ms) 11 : 218/FCH (Approx.26.2 ms) Power-on reset selection With power-on reset Without power-on reset Reset pin output With reset output Without reset output MB89935A Specify when ordering masking MB89P935A MB89PV930A
Setting not possible
1
Selectable
Fixed to 218/FCH (Approx. 26.2 ms)
Fixed to 218/FCH (Approx. 26.2 ms)
2
Selectable
Available
Available
3
Selectable
With reset output
With reset output
FCH : Main clock oscillation frequency *: Initial value to which the oscillation settling time bit (SYCC: WT1, WT0) in the system clock control register is set
s ORDERING INFORMATION
Part number MB89935APFV MB89P935APF MB89PV930ACF Package 30-pin Plastic SSOP (FPT-30P-M02) 48-pin Ceramic MQFP (MQP-48C-P01) Remarks
38
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MB89930A Series
s PACKAGE DIMENSIONS
30-pin plastic LQFP (FPT-30P-M02)
* 9.700.10(.382.004)
* : This dimension does not include resin protrusion.
1.25 -0.10
+0.20 +.008 (Mounting height) .049 -.004 0.10(.004)
INDEX
5.600.10 (.220.004)
7.600.20 (.299.008)
6.60(.260) NOM
0.650.12(.0256.0047)
0.22 -0.05 .009
+0.10 +.004 -.002
"A"
0.15 -0.02 .006 -.001
+0.05 +.002
Details of "A" part 0.100.10(.004.004) (STAND OFF)
9.10(.358)REF 0 10 0.500.20 (.020.008)
C
1994 FUJITSU LIMITED F30003S-2C-3
Dimensions in mm (inches)
(Continued)
39
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MB89930A Series
(Continued) 48-pin ceramic MQFP (MQP-48C-P01)
17.20(.677)TYP 15.000.25 (.591.010) 14.820.35 (.583.014) 1.50(.059)TYP 1.00(.040)TYP 8.80(.346)REF 0.800.22 (.0315.0087) PIN No.1 INDEX
PIN No.1 INDEX
1.020.13 (.040.005)
10.92 -0.0 .430 -0
+0.13 +.005
7.14(.281) 8.71(.343) TYP TYP
PAD No.1 INDEX 0.30(.012)TYP 4.50(.177)TYP 1.10 -0.25 .043 -.010
+0.45 +.018
0.400.08 (.016.003)
0.60(.024)TYP
8.50(.335)MAX
0.150.05 (.006.002)
C
1994 FUJITSU LIMITED M48001SC-4-2
Dimensions in mm (inches)
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MB89930A Series
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9910 (c) FUJITSU LIMITED Printed in Japan

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